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8-channel/4-channel fault-protected analog multiplexers adg508f/ adg509f rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2001C2011 analog devices, inc. all rights reserved. features all switches off with power supply off analog output of on channel clamped within power supplies if an overvoltage occurs latch-up proof construction low on resistance (270 typical) fast switching times t on : 230 ns maximum t off : 130 ns maximum low power dissipation (3.3 mw maximum) fault and overvoltage protection (?40 v to +55 v) break-before-make construction ttl and cmos compatible inputs applications existing multiplexer applications (both fault-protected and nonfault-protected) new designs requiring multiplexer functions general description the adg508f and adg509f are cmos analog multi- plexers, with the adg508f comprising eight single channels and the adg509f comprising four differential channels. these multiplexers provide fault protection. using a series n-channel, p-channel, n-channel mosfet structure, both device and signal source protection is provided in the event of an overvoltage or power loss. the multiplexer can withstand continuous overvolt- age inputs from ?40 v to +55 v. during fault conditions with power supplies off, the multiplexer input (or output) appears as an open circuit and only a few nanoamperes of leakage current will flow. this protects not only the multiplexer and the circuitry driven by the multiplexer, but also protects the sensors or signal sources that drive the multiplexer. the adg508f switches one of eight inputs to a common output as determined by the 3-bit binary address lines a0, a1, and a2. the adg509f switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines a0 and a1. an en input on each device is used to enable or disable the device. when disabled, all channels are switched off. functional block diagrams s1 s8 a0 d adg508f a1 a2 en 1 of 8 decoder 00035-001 figure 1. s1a a0 da adg509f a1 s4a s1b s4b db en 1 of 4 decoder 00035-101 figure 2. product highlights 1. fault protection. the adg508f / adg509f can withstand continuous voltage inputs from ?40 v to +55 v. when a fault occurs due to the power supplies being turned off, all the channels are turned off and only a leakage current of a few nanoamperes flows. 2. on channel saturates while fault exists. 3. low r on . 4. fast switching times. 5. break-before-make switching. switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 6. trench isolation eliminates latch-up. a dielectric trench separates the p and n-channel mosfets thereby preventing latch-up.
adg508f/adg509f rev. f | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagrams............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 dual supply ................................................................................... 3 truth tables................................................................................... 4 absolute maximum ratings ............................................................5 esd caution...................................................................................5 pin configuration and function descriptions..............................6 typical performance characteristics ..............................................8 terminology .................................................................................... 10 theory of operation ...................................................................... 11 test circuits..................................................................................... 12 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 17 revision history 7/11rev. e to rev. f deleted adg528f ..............................................................universal changes to features section and general description section . 1 changes to specifications section.................................................. 3 deleted timing diagrams section ................................................. 4 changes to table 4............................................................................ 5 added table 5.................................................................................... 6 added table 6.................................................................................... 7 replaced typical performance characteristics section .............. 8 changes to terminology section.................................................. 10 changes to figure 27 and figure 28............................................. 13 changes to figure 31...................................................................... 14 changes to theory of operation section.................................... 11 updated outline dimensions ....................................................... 15 changes to ordering guide .......................................................... 17 7/09rev. d: rev. e updated format..................................................................universal added tssop .....................................................................universal updated outline dimensions ....................................................... 15 changes to ordering guide .......................................................... 18 4/01data sheet changed from rev. c to rev. d. changes to ordering guide ............................................................ 1 changes to specifications table...................................................... 2 max ratings changed ...................................................................... 4 deleted 16-lead cerdip from outline dimensions .................. 11 deleted 18-lead cerdip from outline dimensions .................. 12
adg508f/adg509f rev. f | page 3 of 20 specifications dual supply v dd = +15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. b version parameter +25c ?40c to +85c unit test conditions/comments analog switch analog signal range v ss + 1.4 v typ output open circuit v dd ? 1.4 v typ v ss + 2.2 v typ output loaded, 1 ma v dd C 2.2 v typ r on 270 350 typ ?10 v v s +10 v, i s = 1 ma; 390 max v dd = +15 v 10%, v ss = ?15 v 10% see figure 21 r on drift 0.6 %/c typ v s = 0 v, i s = 1 ma on-resistance match between channels, ?r on 3 % max v s = 10 v, i s = ?1 ma leakage currents source off leakage i s (off ) 0.02 na typ v d = 10 v, v s = + 10 v; 1 50 na max see figure 22 drain off leakage i d (off) 0.04 na typ v d = 10 v, v s = + 10 v; adg508f 1 60 na max see figure 23 adg509f 1 30 na max channel on leakage i d , i s (on) 0.04 na typ v s = v d = 10 v; adg508f 1 60 na max see figure 24 adg509f 1 30 na max fault source leakage current i s (fault) 0.02 na typ v s = +55 v or ?40 v, v d = 0 v, see figure 25 (with overvoltage) 2 2 a max drain leakage current i d (fault) 5 na typ v s = 25 v, v d = + 10 v, see figure 23 (with overvoltage) 2 a max source leakage current i s (fault) (power supplies off ) 1 na typ v s = 25 v, v d = v en = a0, a1, a2 = 0 v 2 a max see figure 26 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 1 a max v in = 0 or v dd c in , digital input capacitance 5 pf typ dynamic characteristics 1 t transition 175 ns typ r l = 1 m, c l = 35 pf; 220 300 ns max v s1 = 10 v, v s8 = + 10 v; see figure 27 t open 90 ns typ r l = 1 k, c l = 35 pf; 60 40 ns min v s = 5 v; see figure 28 t on (en) 180 ns typ r l = 1 k, c l = 35 pf; 230 300 ns max v s = 5 v; see figure 29 t off (en) 100 ns typ r l = 1 k, c l = 35 pf 130 150 t sett , settling time ns max v s = 5 v; see figure 29 0.1% 1 s typ r l = 1 k, c l = 35 pf; 0.01% 2.5 s typ v s = 5 v
adg508f/adg509f rev. f | page 4 of 20 b version parameter +25c ?40c to +85c unit test conditions/comments charge injection 15 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 30 off isolation 93 db typ r l = 1 k, c l = 15 pf, f = 100 khz; v s = 7 v rms; see figure 31 c s (off ) 3 pf typ c d (off) adg508f 22 pf typ adg509f 12 pf typ power requirements i dd 0.05 0.2 ma max v in = 0 v or 5 v i ss 0.1 1 a max 1 guaranteed by design, not subject to production test. truth tables table 2. adg508f truth table 1 a2 a1 a0 en on switch x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 1 x = dont care. table 3. adg509f truth table 1 a1 a0 en on switch pair x x 0 none 0 0 1 1 0 1 1 2 1 0 1 3 1 1 1 4 1 x = dont care.
adg508f/adg509f rev. f | page 5 of 20 absolute maximum ratings t a = 25c unless otherwise noted. table 4. parameter rating v dd to v ss 48 v v dd to gnd ?0.3 v to +48 v v ss to gnd +0.3 v to ?48 v digital input, en, ax ?0.3 v to v dd + 0.3 v or 20 ma, whichever occurs first v s , analog input overvoltage with power on (v dd = +15 v, v ss = ?15 v) v ss ? 25 v to v dd + 40 v v s , analog input overvoltage with power off (v dd = 0 v, v ss = 0 v) ?40 v to +55 v continuous current, s or d 20 ma peak current, s or d (pulsed at 1 ms, 10% duty cycle max) 40 ma operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c tssop ja , thermal impedance 112c/w plastic dip package ja , thermal impedance 16-lead 117c/w soic package ja , thermal impedance narrow body 77c/w wide body 75c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adg508f/adg509f rev. f | page 6 of 20 pin configuration and fu nction descriptions a0 1 en 2 v ss 3 s1 4 a1 16 a2 15 gnd 14 v dd 13 s2 5 s3 6 s4 7 s5 12 s6 11 s7 10 d 8 s8 9 adg508f top view (not to scale) 00035-004 figure 3. adg508f pin configuration table 5. adg508f pin function descriptions pin no. nemonic description 1 a0 logic control input. 2 en active high digital input. when low, the device is disabled and all switches are off. when high, ax logic inputs determine on switches. 3 v ss most negative power supply potential. in single-supply applications, this pin can be connected to ground. 4 s1 source terminal 1. this pin can be an input or an output. 5 s2 source terminal 2. this pin can be an input or an output. 6 s3 source terminal 3. this pin can be an input or an output. 7 s4 source terminal 4. this pin can be an input or an output. 8 d drain terminal. this pin can be an input or an output. 9 s8 source terminal 8. this pin can be an input or an output. 10 s7 source terminal 7. this pin can be an input or an output. 11 s6 source terminal 6. this pin can be an input or an output. 12 s5 source terminal 5. this pin can be an input or an output. 13 v dd most positive power supply potential. 14 gnd ground (0 v) reference. 15 a2 logic control input. 16 a1 logic control input.
adg508f/adg509f rev. f | page 7 of 20 a0 1 en 2 v ss 3 s1a 4 a1 16 gnd 15 v dd 14 s1b 13 s2a 5 s3a 6 s4a 7 s2b 12 s3b 11 s4b 10 da 8 db 9 adg509f top view (not to scale) 00035-005 figure 4. adg509f pin configuration table 6. adg509f pin function descriptions pin no. nemonic description 1 a0 logic control input. 2 en active high digital input. when low, the device is disabled and all switches are off. when high, ax logic inputs determine on switches. 3 v ss most negative power supply potential. in single-supply applications, this pin can be connected to ground. 4 s1a source terminal 1a. this pi n can be an input or an output. 5 s2a source terminal 2a. this pi n can be an input or an output. 6 s3a source terminal 3a. this pi n can be an input or an output. 7 s4a source terminal 4a. this pi n can be an input or an output. 8 da drain terminal a. this pin can be an input or an output. 9 db drain terminal b. this pin can be an input or an output. 10 s4b source terminal 4b. this pi n can be an input or an output. 11 s3b source terminal 3b. this pi n can be an input or an output. 12 s2b source terminal 2b. this pi n can be an input or an output. 13 s1b source terminal 1b. this pi n can be an input or an output. 14 v dd most positive power supply potential. 15 gnd ground (0 v) reference. 16 a1 logic control input.
adg508f/adg509f rev. f | page 8 of 20 typical performance characteristics 2000 1000 0 15 ?15 ?10 ?5 0 5 10 500 1750 1500 1250 750 250 v d , v s (v) r on ( ? ) v dd = +15v v ss = ?15v 00035-011 t a = 125c t a = 105c t a = 85c t a = 25c 2000 1000 0 15 ?15 ?10 ?5 0 5 10 500 1750 1500 1250 750 250 v d , v s (v) r on ( ? ) t a = 25c v dd = +5v v ss = ?5v v dd = +10v v ss = ?10v v dd = +15v v ss = ?15v 00035-008 figure 5. on resistance as a function of v d (v s ) figure 8. on resistance as a function of v d (v s ) for different temperatures 1m 1 1p ?50 ?30 ?20 ?10 0 10 20 30 40 50 60 ?40 1n 100 10 10n 100n 10p 100p v s source voltage (v) i s input leakage (a) operating range v dd = 0v v ss = 0v v d = 0v 00035-009 1m 1 1p ?50 ?30 ?20 ?10 0 10 20 30 40 50 60 ?40 1n 100 10 10n 100n 10p 100p v s source voltage (v) i s input leakage (a) operating range v dd = +15v v ss = ?15v v d = 0v 00035-012 figure 6. source input leakage current as a function of v s (power supplies off) during overvo ltage conditions figure 9. source input leakage current as a function of v s (power supplies on) during overvoltage conditions 0.3 0.2 ?0.3 ?14 ?10 ?6 ?2 2 6 10 14 0.1 0.0 ?0.2 ?0.1 v s ,v d (v) leakage currents (na) i d (off) i s (off) i d , i s (on) v dd = +15v v ss = ?15v v s (v d ) = 10v t a = 25c 00035-013 1m 1 1p ?50 ?30 ?20 ?10 0 10 20 30 40 50 60 ?40 1n 100 10 10n 100n 10p 100p v s source voltage (v) i d input leakage (a) operating range v dd = +15v v ss = ?15v v d = 0v 00035-010 figure 10. leakage currents as a function of v d (v s ) figure 7. drain output leakage current as a function of v s (power supplies on) during overvoltage conditions
adg508f/adg509f rev. f | page 9 of 20 100 10 0.01 45 55 25 65 75 85 95 105 35 1 115 125 0.1 temperature (c) leakage currents (na) v dd = +15v v ss = ?15v v d = +10v v s = ?10v i s (off) i d (on) i d (off) 00035-014 figure 11. leakage currents as a function of temperature 260 240 100 10 11 12 13 14 15 120 t on (en) 220 200 180 160 140 switching time (ns) power supply (v) t transition t off (en) 00035-015 figure 12. switching time vs. dual power supply 300 0 ?40 ?20 0 20 40 60 80 100 120 50 250 200 150 100 temperature (c) switching time (ns) 00035-016 t transition t on (en) t off (en) v dd = +15v v ss = ?15v figure 13. switching time vs. temperature ?120 ?100 ?80 ?60 ?40 ?20 0 off isol a tion (db) frequency (hz) 10k 100k 1m 10m 100m 1g 1k 000354-113 t a = 25c v dd = +15v v ss = ?15v figure 14. off isolation vs. frequency, 15 v dual supply 0 5 10 15 20 25 30 35 40 ?15 ?10 ?5 0 5 10 15 pin capacitance (pf) v s (v) t a = 25c v dd = +15v v ss = ?15v drain off source off 00035-114 figure 15. capacitance vs. source voltage ?30 ?20 ?10 0 10 20 30 ?15 ?10 ?5 0 5 10 15 q inj (pc) v s (v) 00035-115 v dd = +15v v ss = ?15v t a = 25c figure 16. charge injection vs. source voltage
adg508f/adg509f rev. f | page 10 of 20 terminology v dd most positive power supply potential. v ss most negative power supply potential. gnd ground (0 v) reference. r on ohmic resistance between d and s. r on drift percentage change in r on when temperature changes by one degree celsius. r on r on represents the difference between the r on of any two channels as a percentage of the maximum r on of those two channels. i s (off) source leakage current when the switch is off. i d (off) drain leakage current when the switch is off. i d , i s (on) channel leakage current when the switch is on. i s (faultpower supplies on) source leakage current when exposed to an overvoltage condition. i d (faultpower supplies on) drain leakage current when exposed to an overvoltage condition. i s (faultpower supplies off) source leakage current with power supplies off. v d (v s ) analog voltage on terminals d, s. c s (off) channel input capacitance for off condition. c d (off) channel output capacitance for off condition. c in digital input capacitance. t on (en) delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) delay time between the 50% and 90% points of the digital input and switch off condition. t transition delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t open off time measured between 80% points of both switches when switching from one address state to another. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. off isolation a measure of unwanted signal coupling through an off channel. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. i dd positive supply current. i ss negative supply current.
adg508f/adg509f rev. f | page 11 of 20 theory of operation the adg508f / adg509f multiplexers are capable of withstand- ing overvoltages from ?40 v to +55 v, irrespective of whether the power supplies are present or not. each channel of the multiplexer consists of an n-channel mosfet, a p-channel mosfet, and an n-channel mosfet, connected in series. when the analog input exceeds the power supplies, one of the mosfets will saturate limiting the current. the current during a fault condition is determined by the load on the output. figure 17 illustrates the channel architecture that enables these multiplexers to withstand continuous overvoltages. when an analog input of v ss + 2.2 v to v dd ? 2.2 v (output loaded, 1 ma) is applied to the adg508f / adg509f , the multiplexer behaves as a standard multiplexer, with spec- ifications similar to a standard multiplexer, for example, the on-resistance is 390 maximum. however, when an overvoltage is applied to the device, one of the three mosfets saturate. figure 17 to figure 20 show the conditions of the three mosfets for the various overvoltage situations. when the analog input applied to an on channel approaches the positive power supply line, the n-channel mosfet saturates because the voltage on the analog input exceeds the difference between v dd and the n-channel threshold voltage (v tn ). when a voltage more nega- tive than v ss is applied to the multiplexer, the p-channel mosfet will saturate because the analog input is more negative than the difference between v ss and the p-channel threshold voltage (v tp ). because v tn is nominally 1.4 v and v tp ?1.4 v, the analog input range to the multiplexer is limited to v ss + 1.4 v to v dd C 1.4 v (output open circuit) when a 15 v power supply is used. when the power supplies are present but the channel is off, again either the p-channel mosfet or one of the n-channel mosfets will remain off when an overvoltage occurs. finally, when the power supplies are off, the gate of each mosfet will be at ground. a negative overvoltage switches on the first n-channel mosfet but the bias produced by the overvoltage causes the p-channel mosfet to remain turned off. with a positive overvoltage, the first mosfet in the series will remain off because the gate to source voltage applied to this mosfet is negative. during fault conditions (power supplies off), the leakage current into and out of the adg508f / adg509f is limited to a few microamps. this protects the multiplexer and succeeding circuitry from over stresses as well as protecting the signal sources which drive the multiplexer. also, the other channels of the multiplexer will be undisturbed by the overvoltage and will continue to operate normally. q1 q2 q3 +55v overvoltage n-channel mosfet saturates v dd v ss 00035-017 figure 17. +55 v overvoltage input to the on channel q1 q2 q3 ?40v overvoltage n-channel mosfet is on p-channel mosfet saturates v ss v dd 00035-018 figure 18. ?40 v overvoltage on an off channel with multiplexer power on q1 q2 q3 +55v overvoltage n-channel mosfet is off 00035-019 figure 19. +55 v overvoltage with power off q1 q2 q3 ?40v overvoltage n-channel mosfet is on p-channel mosfet is off 00035-020 figure 20. ?40 v overvoltage with power off
adg508f/adg509f rev. f | page 12 of 20 test circuits i ds s r on = v 1 /i ds v1 v s d 0 0035-021 figure 21. on resistance s1 s2 s8 v d i s (off) v s v dd v ss v dd v ss d 0.8v en a 00035-022 figure 22. i s (off) s1 s2 s8 v s i d (off) v d v dd v ss v dd v ss d 0.8v en a 00035-023 figure 23. i d (off) 0 0035-025 sd a v d i d (on) nc nc = no connect figure 24. i d (on) s1 s2 s8 v s v d v dd v ss v dd v ss d 0.8v en a 00035-026 figure 25. input leakage current (with overvoltage) a2 0v 0 v v dd v ss v s d 0 v a1 a0 en gnd adg508f s1 s8 a 00035-027 figure 26. input leakage current (with power supplies off)
adg508f/adg509f rev. f | page 13 of 20 a2 v ss v dd d v s1 v in v s8 v out a1 a0 en gnd adg508f* s1 s8 s2 to s7 2.4v 50 ? r l 1m ? c l 35pf v ss v dd *similar connection for adg509f. 3v 50% v out t transition 90% 90% t transition address drive (v in ) 50% 00035-024 figure 27. switching time of multiplexer, t transition a2 v ss v dd d v s v in v out a1 a0 en gnd adg508f* s1 s8 s2 to s7 2.4v 50 ? r l 1k ? c l 35pf v ss v dd address drive (v in ) 3v v out t open 80% 80% * similar connection for adg509f. 00035-029 figure 28. break-before-make delay, t open a2 v ss v dd d v s v out a1 a0 en gnd adg508f* s1 s2 to s8 r l 1k? 50? c l 35pf v ss v dd enable drive (v in ) 3v 0v 0v v out output t on (en) t off (en) 50% 50% 0.9v out 0.1v out *similar connection for adg509f. 00035-030 v in figure 29. enable delay, t on (en), t off (en)
adg508f/adg509f rev. f | page 14 of 20 3v v out logic input (v in ) q inj = c l ? v out 0v a2 v out d *similar connection for adg509f. a1 a0 en gnd adg508f* s c l 1nf v s v ss v ss v dd v dd v in r s ? v out 00035-033 figure 30. charge injection 00035-034 v out 50 ? network analyzer r l 50 ? in v in sa d v s v dd v ss 0.1f v dd 0.1f v ss gnd 50 ? nc sb off isolation = 20 log v out v s figure 31. off isolation
adg508f/adg509f rev. f | page 15 of 20 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001-ab 073106-b 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 16 1 8 9 0.100 (2.54) bsc 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 32. 16-lead plastic dual in-line package [pdip] narrow body (n-16) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ac 10.00 (0.3937) 9.80 (0.3858) 16 9 8 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 060606-a 45 figure 33. 16-lead standard small outline package [soic_n] narrow body (r-16) dimensions shown in millimeters and (inches)
adg508f/adg509f rev. f | page 16 of 20 controlling dimensions are in m illimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 34. 16-lead standard small ou tline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 35. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters
adg508f/adg509f rev. f | page 17 of 20 ordering guide model 1 temperature range package description package option adg508fbnz ?40c to +85c 16-lead pdip n-16 adg508fbrn ?40c to +85c 16-lead soic_n r-16 adg508fbrnz ?40c to +85c 16-lead soic_n r-16 adg508fbrnzCreel7 ?40c to +85c 16-lead soic_n r-16 adg508fbrwz ?40c to +85c 16-lead soic_w rw-16 adg508fbrwz-reel ?40c to +85c 16-lead soic_w rw-16 adg508fbruz ?40c to +85c 16-lead tssop ru-16 adg508fbruz-reel7 ?40c to +85c 16-lead tssop ru-16 adg509fbnz ?40c to +85c 16-lead pdip n-16 adg509fbrn ?40c to +85c 16-lead soic_n r-16 ADG509FBRNZ ?40c to +85c 16-lead soic_n r-16 ADG509FBRNZCreel7 ?40c to +85c 16-lead soic_n r-16 adg509fbrwz ?40c to +85c 16-lead soic_w rw-16 adg509fbrwz-reel ?40c to +85c 16-lead soic_w rw-16 adg509fbruz ?40c to +85c 16-lead tssop ru-16 adg509fbruz-reel7 ?40c to +85c 16-lead tssop ru-16 1 z = rohs compliant part.
adg508f/adg509f rev. f | page 18 of 20 notes
adg508f/adg509f rev. f | page 19 of 20 notes
adg508f/adg509f rev. f | page 20 of 20 notes ?2001C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00035-0-7/11(f)

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